[{"data":1,"prerenderedAt":35},["ShallowReactive",2],{"maker-gergoerdi":3},[4],{"id":5,"name":6,"line":7,"ai":8,"cat":9,"year":10,"points":11,"comments":12,"rec":13,"s":14,"top":15,"kw":16,"maker":22,"domain":23,"tier":24,"attempts":25,"strip":26,"url":27,"mix":28,"praise":32,"objection":33,"sub":34},29313350,"Retrocomputing with Clash","Haskell for FPGA Hardware Design",false,"learning_science",2021,80,31,"curious",0.11,25,[17,18,19,20,21],"clash haskell","fpga","hdl","retrocomputing","hardware design","gergoerdi","unsafeperform.io","notable",0,"0010353333303330510500155300050","https:\u002F\u002Funsafeperform.io\u002Fretroclash\u002F",[29,30,25,31],6,10,3,"Clash is a better language than Verilog\u002FVHDL for hardware design","Verilog\u002FVHDL tooling and vendor support matter more than the language","hardware design book",1793991264358]