[{"data":1,"prerenderedAt":35},["ShallowReactive",2],{"maker-purisame":3},[4],{"id":5,"name":6,"line":7,"ai":8,"cat":9,"year":10,"points":11,"comments":12,"rec":13,"s":14,"top":15,"kw":16,"maker":22,"domain":23,"tier":24,"attempts":25,"strip":26,"url":27,"mix":28,"praise":32,"objection":33,"sub":34},22279308,"HDMI","Open-source, configurable HDMI output for FPGAs",false,"hardware",2020,195,31,"mixed",0.19,10,[17,18,19,20,21],"fpga","hdmi","systemverilog","dvi","video output","purisame","github.com","notable",0,"5030335003000000000300503010155","https:\u002F\u002Fgithub.com\u002Fhdl-util\u002Fhdmi",[29,30,25,31],5,6,2,"Readable, well-written SystemVerilog","HDMI adopter licensing fees may apply to shipped products","fpga video output",1794036770123]