[{"data":1,"prerenderedAt":252},["ShallowReactive",2],{"project-26990615":3},{"id":4,"name":5,"line":6,"line_source":7,"title":8,"url":9,"domain":10,"maker":11,"posted_at":12,"year":13,"points":14,"comments":15,"rank_in_year":16,"shown_in_year":17,"top":18,"tier":19,"category":20,"subcategory":21,"format":22,"keywords":23,"reception":29,"sentiment":30,"stance_mix":31,"scored_comments":36,"aspects":37,"strip":42,"post_text":45,"what":46,"said":68,"maker_in_thread":135,"shape":143,"grid":148,"attempts":213,"same_week":214,"maker_shows":32,"maker_hidden":244,"reader_version":245,"card":246},"26990615","tiny-hdl","A RISC-V core in Racket","title","Show HN: A RISC-V core in Racket","http:\u002F\u002Fguillaume.baierouge.fr\u002F2021\u002F04\u002F23\u002Fsimulating-digital-circuits-in-racket\u002Fa-risc-v-core-in-racket\u002Findex.html","guillaume.baierouge.fr","_mouvantsillage",1619766734,2021,122,27,424,2533,17,"notable","hardware","hdl simulation","library",[24,25,26,27,28],"risc-v","racket","hdl","hardware simulation","verilog","curious",0.083,{"positive":32,"neutral":33,"mixed":34,"critical":35},2,11,1,0,14,{"docs":38,"design":39,"idea":40,"performance":41},{"positive":34,"critical":35},{"positive":35,"critical":35},{"positive":34,"critical":35},{"positive":35,"critical":35},[35,43,44,35,35,35,35,44,44,43,44,35,35,35,35,35,44,44,44,35,35,35,44,44,44,44,44],5,3,null,{"problem":47,"audience":45,"pricing":45,"motivation":54,"time_to_build":45,"stack":58,"openness":67,"stage":67,"team_size":67},{"value":48,"source":49,"evidence":50},"Simulating digital hardware and eventually generating Verilog or VHDL using Racket","maker",[51],{"id":52,"by":11,"text":53},"26990661","Author here. This post is part of an ongoing experiment to use Racket as a platform for hardware description languages. Describing a RISC-V core in Racket is a step in this…",{"value":55,"source":49,"evidence":56},"Explore Racket as a platform for hardware description languages",[57],{"id":52,"by":11,"text":53},[59],{"value":60,"source":61,"evidence":62},"Racket","commenter",[63],{"id":64,"by":65,"text":66},"27006207","senshu","In the \"signal-of-vectors vs vector-of-signals\" comparison, \"vector\" refers to the Racket data type used for arrays. It should not be confused with \"bit vectors\", which are…","unknown",{"praise":69,"objections":85,"requests":97,"questions":105,"alternatives":120},[70],{"value":71,"source":61,"evidence":72},"Impressive, fascinating work",[73,77,81],{"id":74,"by":75,"text":76},"27006594","brandmeyer","Very impressive work. I've only spent about an hour going through this post and its predecessor. I'm a career software engineer, although I've been working very closely with a…",{"id":78,"by":79,"text":80},"27007055","spfzero","Fascinating work, thanks for creating it!",{"id":82,"by":83,"text":84},"27005017","i_don_t_know","This is great! I also like your other posts in the series on tiny-hdl. Thank you for writing this up!",[86],{"value":87,"source":61,"evidence":88},"Formal verification may not catch Spectre-type timing issues",[89,93],{"id":90,"by":91,"text":92},"27008478","mhh__","Spectre isn't really something that you can catch with formal verification. It sort of isn't a bug, that's why it's such a problem.",{"id":94,"by":95,"text":96},"27013915","amelius","Only because most models focus on functionality, not on timing.",[98],{"value":99,"source":61,"evidence":100},"Write-up on place and route and netlist-to-layout algorithms",[101],{"id":102,"by":103,"text":104},"27006094","ampdepolymerase","Can you do a write up on the lower level algorithms like place and route, circuit constraints solving optimization, the process from the netlist stage to autorouting? The…",[106,114],{"value":107,"source":61,"evidence":108},"How signal updates propagate to sensitive processes and performance comparison",[109,113],{"id":110,"by":111,"text":112},"27005801","artemonster","If using \"signal of vector\": how does an update is propagated to a process that is sensitive only to some particular bits? So, any update to that signal (whatever the bit) causes…",{"id":64,"by":65,"text":66},{"value":115,"source":61,"evidence":116},"Similar simple RISC-V cores in Clash or Bluespec",[117],{"id":118,"by":91,"text":119},"27006240","Cool! Is there a similarly simple core to compare with in Bluespec and Clash?",[121,125,129],{"value":122,"source":61,"evidence":123},"Clash",[124],{"id":64,"by":65,"text":66},{"value":126,"source":61,"evidence":127},"Bluespec",[128],{"id":118,"by":91,"text":119},{"value":130,"source":49,"evidence":131},"SymbiYosys formal verification",[132],{"id":133,"by":11,"text":134},"27007623","While simulation is a well-established practice among digital hardware developers, I have the impression that formal verification is still largely ignored. I hope it changes as…",{"comments":136,"answered":44,"key":137},4,[138,139,142],{"id":52,"text":53},{"id":140,"text":141},"27006414","My experience in the lower-level aspects of hardware synthesis is limited but I would love to explore this topic. I use proprietary synthesis tools for FPGAs everyday but I do…",{"id":133,"text":134},{"commenters":144,"max_depth":145,"maker_replies":136,"first_comment_mins":146,"lifespan_hours":147},16,6,7,176,[149,151,153,155,158,161,164,166,170,172,174,177,178,180,182,184,187,189,192,194,196,199,201,204,206,208,210],[52,35,35,150,11,34],"maker\u002Fneutral\u002Fidea",[82,35,43,152,83,35],"maker\u002Fpositive\u002Fdocs",[102,35,44,154,103,35],"maker\u002Fneutral\u002Fdocs",[156,35,35,157,91,35],"27006140","other\u002Fneutral\u002Fnone",[159,35,35,157,160,35],"27006175","User23",[162,35,35,157,163,35],"27021022","monocasa",[140,35,35,165,11,34],"maker\u002Fneutral\u002Fnone",[167,35,44,168,169,35],"27006937","maker\u002Fneutral\u002Fdesign","mainland",[171,35,44,168,65,35],"27007504",[78,35,43,173,79,35],"project\u002Fpositive\u002Fidea",[175,35,44,176,95,35],"27007207","project\u002Fneutral\u002Fidea",[133,35,35,150,11,34],[90,35,35,179,91,35],"other\u002Fneutral\u002Fprivacy",[94,35,35,181,95,35],"commenter\u002Fneutral\u002Fnone",[183,35,35,181,91,35],"27014896",[185,35,35,181,186,35],"27076666","sitkack",[74,34,44,188,75,35],"project\u002Fmixed\u002Fidea",[190,34,44,176,191,35],"27008076","akiselev",[193,34,44,176,83,35],"27009392",[195,34,35,181,75,35],"27009830",[197,34,35,198,11,34],"27010376","commenter\u002Fneutral\u002Fidea",[200,34,35,181,75,35],"27010643",[202,32,44,176,203,35],"27009236","tn1",[110,44,44,205,111,35],"project\u002Fneutral\u002Fperformance",[64,44,44,207,65,35],"maker\u002Fneutral\u002Fperformance",[118,136,44,209,91,35],"project\u002Fneutral\u002Fnone",[211,136,44,209,212,35],"27009602","nereye",[],[215,220,224,229,234,239],{"id":216,"name":217,"points":218,"category":219},"26998308","Second-Chance Pool",543,"consumer_social",{"id":221,"name":222,"points":223,"category":219},"27034904","Boze",450,{"id":225,"name":226,"points":227,"category":228},"27050801","Building Mobile Apps at Scale",357,"learning_science",{"id":230,"name":231,"points":232,"category":233},"27054357","CS Weapons",245,"games",{"id":235,"name":236,"points":237,"category":238},"27029776","I built Grafar",212,"languages",{"id":240,"name":241,"points":242,"category":243},"27007844","git-split-diffs",178,"dev_tools",false,"v2",{"id":247,"name":5,"line":6,"ai":244,"cat":20,"year":13,"points":14,"comments":15,"rec":29,"s":248,"top":18,"kw":249,"maker":11,"domain":10,"tier":19,"attempts":35,"strip":250,"url":9,"mix":251,"praise":71,"objection":87,"sub":21},26990615,0.08,[24,25,26,27,28],"053000033530000033300033333",[32,33,34,35],1794036606272]