[{"data":1,"prerenderedAt":297},["ShallowReactive",2],{"project-29313350":3},{"id":4,"name":5,"line":6,"line_source":7,"title":8,"url":9,"domain":10,"maker":11,"posted_at":12,"year":13,"points":14,"comments":15,"rank_in_year":16,"shown_in_year":17,"top":18,"tier":19,"category":20,"subcategory":21,"format":22,"keywords":23,"reception":29,"sentiment":30,"stance_mix":31,"scored_comments":36,"aspects":37,"strip":44,"post_text":46,"what":47,"said":97,"maker_in_thread":186,"shape":193,"grid":197,"attempts":258,"same_week":259,"maker_shows":40,"maker_hidden":289,"reader_version":290,"card":291},"29313350","Retrocomputing with Clash","Haskell for FPGA Hardware Design","title","Show HN: Retrocomputing with Clash: Haskell for FPGA Hardware Design","https:\u002F\u002Funsafeperform.io\u002Fretroclash\u002F","unsafeperform.io","gergoerdi",1637628083,2021,80,31,632,2533,25,"notable","learning_science","hardware design book","other",[24,25,26,27,28],"clash haskell","fpga","hdl","retrocomputing","hardware design","curious",0.106,{"positive":32,"neutral":33,"mixed":34,"critical":35},6,10,0,3,19,{"idea":38,"execution":41,"performance":43},{"positive":39,"critical":40},4,1,{"positive":40,"critical":42},2,{"positive":34,"critical":34},[34,34,40,34,35,45,35,35,35,35,35,34,35,35,35,34,45,40,34,45,34,34,40,45,45,35,34,34,34,45,34],5,null,{"problem":48,"audience":58,"pricing":46,"motivation":67,"time_to_build":46,"stack":74,"openness":95,"stage":96,"team_size":95},{"value":49,"source":50,"evidence":51},"Teaching hardware design with a Haskell-based HDL by building retro computers","maker",[52,55],{"id":53,"by":11,"text":54},"29314790","Your website is of course referenced in the Compucolor II chapter of the book. It was invaluable in getting my Compucolor II implementation working. In fact, I even sent you a PR…",{"id":56,"by":11,"text":57},"29313649","In the book (see the sample chapter 8 at https:\u002F\u002Funsafeperform.io\u002Fretroclash\u002F#samples) we create a proto-almost-game (just a bouncing ball) first by directly wiring together…",{"value":59,"source":60,"evidence":61},"Readers learning FPGA hardware design, including Haskell programmers","inferred",[62,66],{"id":63,"by":64,"text":65},"29318612","exdsq","I'm looking at it through another lens - a way to improve my intermediate haskell and learn about HDL. Maybe they're pushing for commercial use but there are alternative reasons…",{"id":56,"by":11,"text":57},{"value":68,"source":60,"evidence":69},"Teach hardware design in Haskell via retro computer projects",[70,71],{"id":53,"by":11,"text":54},{"id":72,"by":11,"text":73},"29316998","Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled…",[75,79,83,91],{"value":76,"source":50,"evidence":77},"Haskell",[78],{"id":72,"by":11,"text":73},{"value":80,"source":50,"evidence":81},"Clash",[82],{"id":72,"by":11,"text":73},{"value":84,"source":85,"evidence":86},"Verilog","commenter",[87],{"id":88,"by":89,"text":90},"29316957","gnull","Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality. > the choice of HDL (which was 95% of the time, Verilog, for the…",{"value":92,"source":50,"evidence":93},"Intel 8080",[94],{"id":53,"by":11,"text":54},"unknown","launched",{"praise":98,"objections":117,"requests":141,"questions":158,"alternatives":172},[99,106,110],{"value":100,"source":85,"evidence":101},"Clash is a better language than Verilog\u002FVHDL for hardware design",[102,103],{"id":88,"by":89,"text":90},{"id":104,"by":89,"text":105},"29327930","I'm trying to look at one specific component here, the language itself. My claim is that as a language Clash is way better than SystemVerilog. True, Verilog has more mature…",{"value":107,"source":50,"evidence":108},"Debugging via high-level simulation is well covered in the book",[109],{"id":72,"by":11,"text":73},{"value":111,"source":85,"evidence":112},"Good Compucolor II chapter choice for the book",[113],{"id":114,"by":115,"text":116},"29314693","tasty_freeze","It was an interesting choice to include the Compucolor II emulation. It was a very quirky machine with some interesting design choices, but not very popular. Ops website…",[118,132,137],{"value":119,"source":85,"evidence":120},"Verilog\u002FVHDL tooling and vendor support matter more than the language",[121,125,128],{"id":122,"by":123,"text":124},"29315204","laydn","I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 95% of the time,…",{"id":126,"by":123,"text":127},"29318465","It's not that we have a low standard, it's that we are bound by the full suite of tools that are provided to us in order to achieve our design objective. When I am close to…",{"id":129,"by":130,"text":131},"29327030","Taniwha","As the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains -…",{"value":133,"source":85,"evidence":134},"Clash ecosystem lacks vendor tool integration for tapeout",[135,136],{"id":129,"by":130,"text":131},{"id":126,"by":123,"text":127},{"value":138,"source":85,"evidence":139},"New HDLs seem unnecessary compared to Verilog",[140],{"id":122,"by":123,"text":124},[142,148],{"value":143,"source":85,"evidence":144},"Explain Clash debug and design flow for Xilinx FPGAs",[145],{"id":146,"by":123,"text":147},"29316477","But, HOW do you debug Clash? For example, what is the design and debug flow of using Clash to target a Xilinx FPGA? My guess is that you're going to tell me I will have to debug…",{"value":149,"source":85,"evidence":150},"Clarify how Clash relates to HLS and Chisel",[151,155],{"id":152,"by":153,"text":154},"29323785","rowanG077","Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not \"higher level\" then VHDL or Verilog. In some…",{"id":156,"by":153,"text":157},"29327560","Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of…",[159,166],{"value":160,"source":85,"evidence":161},"How does Clash compile to bitstream if it generates Verilog",[162],{"id":163,"by":164,"text":165},"29326554","tubby12345",">Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?",{"value":167,"source":85,"evidence":168},"Does Clash match HLS resource overhead",[169],{"id":170,"by":164,"text":171},"29321688","qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?",[173,182],{"value":174,"source":85,"evidence":175},"Chisel",[176,179],{"id":177,"by":164,"text":178},"29327647","got it - it's like chisel. thanks",{"id":180,"by":153,"text":181},"29329875","Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL\u002FVerilog. Clash is a compiler closely based on GHC that…",{"value":183,"source":85,"evidence":184},"Verilog and VHDL",[185],{"id":122,"by":123,"text":124},{"comments":39,"answered":40,"key":187},[188,189,190],{"id":53,"text":54},{"id":72,"text":73},{"id":191,"text":192},"29313362","Previous discussion on HN about Clash itself: https:\u002F\u002Fnews.ycombinator.com\u002Fitem?id=23096338 https:\u002F\u002Fnews.ycombinator.com\u002Fitem?id=9516217",{"commenters":194,"max_depth":195,"maker_replies":39,"first_comment_mins":42,"lifespan_hours":196},11,12,55,[198,200,202,204,207,209,212,214,216,217,218,219,222,223,225,227,229,231,233,236,238,240,242,243,244,245,248,249,252,253,256],[114,34,34,199,115,34],"other\u002Fneutral\u002Fnone",[53,34,34,201,11,40],"project\u002Fpositive\u002Fdocs",[122,40,40,203,123,34],"project\u002Fcritical\u002Fidea",[205,40,34,206,153,34],"29315931","commenter\u002Fpositive\u002Fidea",[146,40,35,208,123,34],"project\u002Fneutral\u002Fexecution",[210,40,45,211,153,34],"29316536","project\u002Fpositive\u002Fexecution",[170,40,35,213,164,34],"project\u002Fneutral\u002Fperformance",[152,40,35,215,153,34],"project\u002Fneutral\u002Fidea",[163,40,35,215,164,34],[156,40,35,215,153,34],[177,40,35,215,164,34],[220,40,34,221,153,34],"29328002","commenter\u002Fneutral\u002Fnone",[180,40,35,215,153,34],[224,40,35,215,164,34],"29334038",[226,40,35,215,153,34],"29339081",[72,40,34,228,11,40],"maker\u002Fpositive\u002Fdocs",[88,40,45,230,89,34],"project\u002Fpositive\u002Fidea",[126,40,40,232,123,34],"project\u002Fcritical\u002Fexecution",[234,40,34,199,235,34],"29319067","typon",[237,40,45,230,89,34],"29320878",[239,40,34,221,164,34],"29321488",[241,40,34,221,89,34],"29321841",[129,40,40,232,130,34],[104,40,45,230,89,34],[63,40,45,230,64,34],[246,40,35,215,247,34],"29339111","qwerty456127",[191,42,34,199,11,40],[250,35,34,199,251,34],"29313589","xupybd",[56,35,34,228,11,40],[254,39,45,255,64,34],"29313779","maker\u002Fpositive\u002Fnone",[257,45,34,199,247,34],"29339126",[],[260,265,270,275,280,285],{"id":261,"name":262,"points":263,"category":264},"29278180","Pony",693,"consumer_social",{"id":266,"name":267,"points":268,"category":269},"29288618","Cleanvoice",221,"creative",{"id":271,"name":272,"points":273,"category":274},"29305643","Repl (CheerpX demo)",171,"dev_tools",{"id":276,"name":277,"points":278,"category":279},"29329610","Ory Kratos",107,"security_privacy",{"id":281,"name":282,"points":283,"category":284},"29284296","WildCard",101,"languages",{"id":286,"name":287,"points":288,"category":274},"29321748","Tamagui",88,false,"v2",{"id":292,"name":5,"line":6,"ai":289,"cat":20,"year":13,"points":14,"comments":15,"rec":29,"s":293,"top":18,"kw":294,"maker":11,"domain":10,"tier":19,"attempts":34,"strip":295,"url":9,"mix":296,"praise":100,"objection":119,"sub":21},29313350,0.11,[24,25,26,27,28],"0010353333303330510500155300050",[32,33,34,35],1793991036499]